Substrate assembly, method of testing the substrate assembly, electrooptical device, method of manufacturing the electrooptical device, and electronic equipment

ABSTRACT

The present invention provides a systems and methods to perform an electrical test on a substrate assembly used as a TFT array substrate of a liquid-crystal device without detaching a mounted external IC. The substrate assembly can include a substrate, a peripheral circuit embedded in the substrate, a first wiring arranged on the substrate, and an external IC, mounted on the substrate, and having a first terminal connected to an interconnection portion arranged on the first wiring. The substrate assembly can further include a second wiring which extends from the interconnection portion in such a manner that the second wiring is routed in a portion of the substrate facing the integrated circuit, and a first external circuit connection terminal arranged on the second wiring in a portion of the substrate not facing the integrated circuit. The external IC is thus tested through the external circuit connection terminal.

This is a Divisional of U.S. patent application Ser. No. 10/166,281filed on Jun. 11, 2002, which is hereby incorporated by reference in itsentirety. This application claims priority to Japanese PatentApplication Nos. 2001-179101 filed Jun. 13, 2001, 2001-179042 filed Jun.13, 2001 and 2002-122815 filed Apr. 24, 2002, which is herebyincorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a technical field of a substrateassembly that can be used as a TFT array substrate in an electroopticaldevice, such as a liquid-crystal device, and of an electrical testmethod of the substrate assembly. The present invention additionallyrelates to a technical field of an electrooptical device, such as aliquid-crystal device including such a substrate, of a manufacturingmethod of manufacturing the electrooptical device, and of a variety ofpieces of electronic equipment including the electrooptical device.

2. Description of Related Art

In an electrooptical device, such as a thin-film transistor (TFT)driving liquid-crystal device, a thin-film transistor usinghigh-temperature polysilicon, low-temperature polysilicon, or amorphoussilicon, as a semiconductor layer is embedded in each pixel forswitching controlling of the pixel on an insulator such as a glasssubstrate or a quartz substrate.

The polysilicon TFTs are generally excellent in transistorcharacteristics and power consumption. For this reason, satisfactorytransistor characteristics and low power consumption features result ifa peripheral circuit composed of such polysilicon TFTs is embedded in aperipheral area surrounding an image display area within which a numberof pixel electrodes are arranged. The arrangement is advantageousbecause the TFTs within the image display area for pixel switching andTFTs forming the peripheral circuit are concurrently produced in thesame manufacturing process.

On the other hand, the amorphous type TFTs are generally outperformed intransistor characteristics and power consumption properties by thepolysilicon TFTs. For this reason, the peripheral circuit, fabricated ofthe amorphous silicon TFTs, typically fails to achieve satisfactorytransistor characteristics and low power consumption. When the amorphoussilicon TFTs are adopted as a pixel switching TFT, a technique in whichan external integrated circuit (IC) is mounted in a peripheral area iswidely accepted.

SUMMARY OF THE INVENTION

According to studies, the technique to embed a peripheral circuitfabricated of the above-mentioned polysilicon TFT has difficulty inembedding a peripheral circuit meeting a high driving frequencyrequirement and a low-power consumption requirement. Such requirementsare typically imposed by high definition display image. For this reason,preferably, an external IC is mounted in a peripheral area, and part ofthe function of the peripheral circuit is thus shouldered by thisexternal IC. For example, a technique disclosed in Japanese UnexaminedPatent Application Publication 04-242724 is known.

If the external integrated circuit is further mounted on a substrate inwhich the peripheral circuit is already embedded as discussed, itbecomes extremely difficult to identify which one of the peripheralcircuit and the external IC is faulty or malfunctions when any of theperipheral circuit and the external IC is faulty or malfunctions afterproduction or shipment. In case of the fault or malfunction, theexternal IC is detached from the substrate, and electrical examinationsmust be performed on the external IC alone. This method isimpracticable.

The technique to mount the external IC on the substrate having theperipheral circuit embedded therewithin has not advanced in practice.

Another problem facing the external IC is that if the external IC ismounted on the peripheral area, a relatively wide peripheral area isrequired to accommodate a variety of above-mentioned trace patterns fortesting, evaluating, and monitoring the manufacturing process, and theexternal IC. A significant portion of the limited area of the substrateis occupied by these trace patterns and the external IC. As a result, itbecomes difficult to meet the general requirements that the substrate becompact while enlarging the image display area within the limitedsubstrate area.

If the external IC is mounted on the substrate in which the peripheralcircuit is embedded, on the other hand, a significant portion of thelimited area of the substrate is also occupied by the peripheral circuitand the external IC. As a result, it also becomes difficult to meet thegeneral requirements that the substrate be compact while enlarging theimage display area within the limited substrate area.

For this reason, no significant advances have been made in the techniqueto mount the external IC on the substrate in which a variety of tracepatterns for testing, evaluating and monitoring the manufacturingprocess, and the peripheral circuit are embedded.

In view of the above problems, the present invention has been developed.It is thus an object of the present invention to provide a substrateassembly which is electrically tested without detaching the external ICtherefrom while enjoying the advantage of a peripheral circuit and theadvantage of an external IC. It is a further object of the presentinvention to provide a test method of the substrate assembly throughwhich the substrate assembly is relatively easily subjected to theelectrical test, an electrooptical device including the substrateassembly, and electronic equipment including the electrooptical device.

In view of the above problems, the present invention has been developed.It is an object of the present invention to provide an electroopticaldevice which assures a wide image display area within the limited areaof the substrate, a manufacturing method of the electrooptical device,and electronic equipment including the electrooptical device.

To achieve the above-referenced problems, a substrate assembly of thepresent invention can include a substrate, a peripheral circuit embeddedin the substrate, a first wiring arranged on the substrate, and anintegrated circuit having a first terminal connected to aninterconnection portion arranged on the first wiring on the substrate.The invention can further include a second wiring which extends from theinterconnection portion in such a manner that the second wiring isrouted in a portion of the substrate facing the integrated circuit, anda first external circuit connection terminal arranged on the secondwiring in a portion of the substrate not facing the integrated circuit.

In accordance with the substrate assembly of the present invention, theperipheral circuit is embedded in the substrate, and the integratedcircuit is then mounted on the substrate. The peripheral circuit is thusembedded in the same manufacturing process as that of a thin-filmtransistor when the thin-film transistor using high-temperaturepolysilicon, low-temperature polysilicon, or amorphous silicon as asemiconductor layer is formed on the substrate. On the other hand, anintegrated circuit manufactured of a transistor outperforming the firstthin-film transistor in switching characteristics and power consumptionis mounted on the substrate. A portion of the function required of acircuit on the substrate is shouldered by the peripheral circuit, whilethe other portion of the function required of the circuit on thesubstrate is shouldered by the integrated circuit mounted on the samesubstrate. In this way, the major advantages of the peripheral circuit,namely, a simple manufacturing process and a simple laminate structure,a compact design and the major advantages of the integrated circuit,namely, high performance and low power consumption, are enjoyed in awell balance.

The first terminal of the integrated circuit is connected to theinterconnection portion arranged on the first wiring, and the secondwiring extends from the interconnection portion in such a manner thatthe second wiring is routed in the portion of the substrate facing theintegrated circuit. The first external circuit connection terminal isarranged on the second wiring in the portion of the substrate not facingthe integrated circuit. Since the first external circuit connectionterminal connected to the first terminal of the integrated circuitthrough the second wiring is arranged clear of the integrated circuit onthe substrate, any signal is exchanged between the integrated circuitand an external test instrument through the first external circuitconnection terminal. For example, if the first terminal serves as anoutput terminal of the integrated circuit, the output characteristics ofthe integrated circuit are tested at the first external circuitconnection terminal using the external text instrument.

Even if the peripheral circuit and the integrated circuit coexist on thesame substrate, it is not necessary to detach the integrated circuitwhen a fault or malfunction is found after the integrated circuit ismounted. It is possible to pick up a signal output from the integratedcircuit, and it is possible to determine which one of the peripheralcircuit and the integrated circuit is faulty. In other words, detachingthe integrated circuit and bringing a test probe to the output terminalare not necessary during test. This arrangement is very useful fortesting the substrate assembly.

The substrate assembly of the present invention enjoys both theadvantages of the peripheral circuit and the advantages of theintegrated circuit while allowing electrical tests to be performedwithout the need for detaching the integrated circuit.

In one embodiment of the present invention, the interconnection portionmay be an interconnection pad arranged on the substrate. In accordancewith this embodiment, by connecting the first terminal of the integratedcircuit to the interconnection portion, namely, the interconnection pad,a reliable electrical connection is relatively easily established.

In another embodiment of the present invention, the substrate assemblymay include a third wiring routed through the portion of the substratefacing the integrated circuit, and a second external circuit connectionterminal arranged on the third wiring in the portion of the substratenot facing the integrated circuit. Further, the integrated circuit canadditionally include a second terminal, which is connected to anotherinterconnection portion arranged on the third wiring. In accordance withthis embodiment of the present invention, the second terminal of theintegrated circuit can be connected to the interconnection portion, suchas the interconnection pad arranged on the third wiring, and isconnected to the second external circuit connection terminal through thethird wiring. Since the second external circuit connection terminalconnected to the second terminal of the integrated circuit is arrangedclear of the integrated circuit on the substrate, any signal isexchanged between the integrated circuit and an external device throughthe second external circuit connection terminal after the integratedcircuit is mounted on the substrate. For example, when the secondterminal is used as an input terminal, a variety of signals such as avideo signal, a control signal, and a power source signal are input tothe second external circuit connection terminal, thereby to theintegrated circuit.

In this embodiment, preferably, the first terminal may be an outputterminal of the integrated circuit, the second terminal may be an inputterminal of the integrated circuit, the first external circuitconnection terminal may be a test terminal for picking up an outputsignal from the integrated circuit, and the second external circuitconnection terminal may be a drive terminal for inputting a variety ofsignals for operating the substrate assembly. In this arrangement, avariety of signals can be fed to the integrated circuit at the secondexternal circuit connection terminal, while an output of the integratedcircuit may be tested at the first external circuit connection terminal.

In the embodiment in which the integrated circuit has the first terminaland the second terminal, the first terminal and the second terminal maybe positioned on the surface of the integrated circuit facing thesubstrate. Although in this arrangement, the input terminal and theoutput terminal arranged on the surface of the integrated circuit facingthe substrate are hidden below the package of the integrated circuitafter the integrated circuit is mounted, the output of the integratedcircuit is tested at the first external circuit connection terminal fromoutside.

It should be understood that any mounting method of the integratedcircuit applicable in this invention may be used, such as a wire bondingmethod, a flipchip method, a beam lead method, besides COG (Chip onGlass) method, and with such a mounting method, the integrated circuitin any of a DIP package, a flatpack package, a chip-carrier package andthe like. This arrangement allows the integrated circuit to be testedthrough the first external circuit connection terminal even after theintegrated circuit is mounted. Since the first terminal or the secondterminal is hidden in the above-referenced integrated circuit, thepresent invention is particularly useful.

A plurality of first terminals and a plurality of second terminals maybe arranged and positioned in a zigzag configuration on the surface ofthe integrated circuit facing the substrate. In this arrangement, thesecond wiring is extended toward the second terminal in perpendicular tothe alignment of the first terminal on the substrate. In this way, theend of the second wiring runs between adjacent second terminals andreaches the opposite side of the second terminal. The second wirings andthe third wirings alternate with each other while reaching the first andsecond external connection terminals.

The first and second external circuit connection terminals may bearranged in a zigzag fashion. In this arrangement, the first and secondexternal circuit connection terminals do not overlap each other even ifthe area of each of them is expanded.

A plurality of first terminals and a plurality of second terminals maynot be arranged in a zigzag fashion. The second wiring may be arrangedin a planar trace pattern evading the first wiring and the secondterminal. A plurality of first external circuit connection terminals anda plurality of second external circuit connection terminals may bearranged in a line.

In yet another embodiment of the substrate assembly of the presentinvention, the peripheral circuit may include a polysilicon thin-filmtransistor. Because of its high-temperature or low-temperaturepolysilicon thin-film transistor in this embodiment, the peripheralcircuit has relatively excellent transistor characteristics and lowpower consumption while the integrated circuit becomes excellent intransistor characteristics and power consumption. A driving circuithaving a very excellent performance as a whole is provided by theperipheral circuit and the integrated circuit.

In one embodiment of the substrate assembly of the present invention,another integrated circuit instead of the peripheral circuit is mountedon the substrate.

In this embodiment, the function of the driving circuit required of thesubstrate assembly is shouldered by two integrated circuits, and theflexibility of design is increased.

To resolve the aforementioned problems, a test method of testing theabove-referenced substrate assembly of the present invention (includingthe embodiments thereof) includes a step of bringing a test probe intocontact with the first external circuit connection terminal after theintegrated circuit is connected to the substrate, and a test step ofperforming an electrical testing on the integrated circuit through thetest probe.

In accordance with the test method of the substrate assembly of thepresent invention, subsequent to the manufacture or shipment of thesubstrate assembly, the test probe is put into contact with the firstexternal circuit connection terminal, and then an electrical test iscarried out on the integrated circuit through the test probe. Theelectrical test is very easily conducted on the integrated circuitthrough the test probe without the need for detaching the integratedcircuit for test purposes.

In another embodiment, the test method of the present invention fortesting the substrate assembly may further include another test step ofperforming an electrical test on the peripheral circuit before theintegrated circuit is mounted to the substrate.

In accordance with this embodiment, the test probe is brought intocontact with the first external circuit connection terminal connected tothe peripheral circuit, or another external circuit connection terminalconnected to the peripheral circuit in the middle of the manufacturingprocess of the substrate assembly prior to the mounting of theintegrated circuit. The peripheral circuit is thus electrically testedthrough the test probe. Prior to the mounting of the integrated circuit,the peripheral circuit is electrically tested, and subsequent to themounting of the integrated circuit, the integrated circuit iselectrically tested through the first external circuit connectionterminal.

To resolve the aforementioned problems, a first electrooptical device ofthe present invention can include, on the substrate assembly (includingthe embodiments thereof), a pixel electrode, a thin-film transistorconnected to the pixel electrode, and a data line and a scanning linerespectively connected to the thin-film transistor, wherein each of theperipheral circuit and the integrated circuit includes a portion of acircuit for driving the data line and the scanning line.

The first electrooptical device of the present invention performsso-called active-matrix driving in which a pixel electrode isswitch-controlled by the thin-film transistor through the data line andthe scanning line. A data line driving circuit and a scanning linedriving circuit for respectively driving the data line and the scanningline are partly included in the peripheral circuit, and partly includedin the integrated circuit. The thin-film transistor forming theperipheral circuit is manufactured in the same manufacturing process asthat of the thin-film transistor for control-switching the pixelelectrode. Specifically, the major advantages of the peripheral circuit,namely, a simple manufacturing process, a simple laminate structure, anda compact design are promoted. Furthermore, the major advantages of theintegrated circuit, namely, high performance and low power consumption,are promoted. With the substrate assembly of the present invention asdiscussed above, the integrated circuit is tested through the firstexternal circuit connection terminal from outside even when theintegrated circuit is mounted on the substrate.

In one embodiment of the first electrooptical device of the presentinvention, the peripheral circuit and the integrated circuit can bearranged in a peripheral area surrounding an image display area withinwhich a plurality of pixel electrodes are arranged.

In accordance with this embodiment, the substrate assembly contains theperipheral circuit and the integrated circuit as the peripheralcircuits.

In another embodiment of the first electrooptical device of the presentinvention, the peripheral circuit may include a sampling switch circuitconnected to the data line, wherein the integrated circuit includes adriving circuit, having a shift register, for driving the data line andthe scanning line.

In accordance with this embodiment, the driving circuit having the shiftregister contained in the integrated circuit drives the data line andthe scanning line, and the sampling circuit contained in the peripheralcircuit samples the video signal. A high-quality image is thus presentedon the screen.

To resolve the aforementioned problems, a second electrooptical deviceof the present invention can include, on a substrate, a pixel electrode,at least one of a wiring and an electronic element for driving the pixelelectrode, an integrated circuit which, mounted on the substrate, formsat least a portion of a driving circuit connected to at least the one ofthe wiring and the electronic element, and a predetermined tracepatterns arranged beneath the integrated circuit.

In accordance with the second electrooptical device of the presentinvention, the pixel electrode is driven in an active-matrix drivingmethod or a passive-matrix driving method by the driving circuit throughthe wirings such as the scanning line, the data line, and a capacitiveline, and the electronic elements such as the thin-film transistor, thethin-film diode, and the storage capacitor. At least a portion of thedriving circuit can be formed of the integrated circuit mounted on thesubstrate. When the electronic element is fabricated of a thin-filmtransistor with amorphous silicon, low-temperature polysilicon, orhigh-temperature polysilicon used as a semiconductor layer, a variety ofperformances, including switching performance and low-power consumption,is substantially improved, compared with the case in which the drivingcircuit is formed of the peripheral circuit which is embedded in thesame manufacturing process of the thin-film transistor.

Arranged beneath the integrated circuit are predetermined trace patternsincluding an evaluation trace pattern of the manufacturing process,which can be optically or visually monitored prior to the mounting ofthe integrated circuit, a test trace pattern for testing themanufacturing process, a monitoring trace pattern for monitoring themanufacturing process, and a trace pattern for evaluating the electronicelement. Since the integrated circuit overlaps the predetermined tracepatterns, an area occupied by the predetermined trace patterns and theintegrated circuit is accordingly reduced. The image display area withinwhich the electrode pixels are arranged becomes relatively large in thelimited area of the substrate.

The predetermined trace patterns may be used in the manufacturingprocess prior to the mounting of the integrated circuit, while not beingused subsequent to the mounting of the integrated circuit. In thisarrangement, the predetermined trace patterns are deployed in the majorportion of the mounting area of the integrated circuit. Since thepredetermined trace patterns thus formed are not used subsequent to themounting of the integrated circuit, the area of the predetermined tracepatterns and the mounting area of the integrated circuit can fullyoverlap each other. The space occupied by the predetermined tracepatterns and the integrated circuit on the substrate is efficientlyreduced.

In yet another embodiment of the second electrooptical device of thepresent invention, the predetermined trace patterns may include at leastone of a trace pattern for evaluating a manufacturing process, a tracepattern for testing the manufacturing process, a trace pattern formonitoring the manufacturing process, and a trace pattern for evaluatingthe electronic element, while being formed in an area of the substrateother than an interconnection pad to which the input and outputterminals of the external integrated circuit are connected.

At least one of the trace pattern for evaluating the manufacturingprocess, the trace pattern for testing the manufacturing process, thetrace pattern for monitoring the manufacturing process, and the tracepattern for evaluating the electronic element, is formed in the areaother than the interconnection pads to which the input and outputterminals of the integrated circuit are connected. The manufacturingprocess is evaluated, tested, and monitored using the predeterminedtrace patterns until a manufacturing step immediately prior to themounting of the integrated circuit.

To resolve the aforementioned problems, a third electrooptical device ofthe present invention can include, on a substrate, a pixel electrode, atleast one of a wiring and an electronic element for driving the pixelelectrode, an integrated circuit which, mounted on the substrate, formsat least a portion of a driving circuit connected to at least the one ofthe wiring and the electronic element, and a bottom circuit arrangedbeneath the integrated circuit and embedded together with at least theone of the wiring and the electronic element.

In accordance with the third electrooptical device of the presentinvention, the pixel electrode can be driven in an active-matrix drivingmethod or a passive-matrix driving method by the driving circuit throughthe wirings, such as the scanning line, the data line, and a capacitiveline, and the electronic elements, such as the thin-film transistor, thethin-film diode, and the storage capacitor. At least a portion of thedriving circuit can be formed of the integrated circuit mounted on thesubstrate. When the electronic element is fabricated of a thin-filmtransistor with amorphous silicon, low-temperature polysilicon, orhigh-temperature polysilicon used as a semiconductor layer, a variety ofperformances, including switching performance and low-power consumption,is substantially improved, compared with the case in which the drivingcircuit is formed of the peripheral circuit which is embedded in thesame manufacturing process of the thin-film transistor. A portion of thedriving circuit and the bottom circuit, such as the test circuit, arearranged beneath the integrated circuit. Since the integrated circuitoverlaps the bottom circuit, an area occupied by the bottom circuit andthe integrated circuit is accordingly reduced. The image display areawithin which the electrode pixels are arranged becomes relatively largein the limited area of the substrate.

In one embodiment of the third electrooptical device of the presentinvention, the integrated circuit may form a portion of the drivingcircuit, and the bottom circuit may form the other portion of thedriving circuit. Since the one portion of the driving circuit containedin the integrated circuit and the other portion of the driving circuitcontained in the bottom circuit overlap each other within the area ofthe substrate in accordance with this embodiment, the image display areabecomes relatively large within the limited area of the substrate.

The wiring may include a data line and a scanning line, the integratedcircuit may include a data line driving circuit for driving the dataline, and the bottom circuit may include a scanning line driving circuitfor driving the scanning line and a sampling circuit for sampling avideo signal and supplying the data line with the sampled video signal.

In this arrangement, a high-performance integrated circuit isresponsible for the data line driving circuit having a high drivingfrequency and high switching characteristics, and the bottom circuit isresponsible for the scanning line driving circuit and the samplingcircuit, each having a low driving frequency and a modestly highswitching performance. Generally, performance imbalance is reduced whilethe image display area is efficiently expanded.

In yet another embodiment of the third electrooptical device of thepresent invention, the bottom circuit may include a test circuit. Inaccordance with this embodiment, the test circuit for testing theelectronic element, the wiring, and the bottom circuit formed on thesubstrate is arranged beneath the integrated circuit. Prior to themounting of the integrated circuit, the electronic element, the wiring,the bottom circuit, etc. can be tested using the test circuit. After theintegrated circuit is mounted, the test circuit may end its usefulness.However, if the input and output terminals of the integrated circuit areinstalled clear of the integrated circuit on the substrate, the testcircuit is still used even after the integrated circuit is mounted.

In a still further embodiment of the third electrooptical device of thepresent invention, the electronic element may include a thin-filmtransistor connected to the pixel electrode, and the bottom circuit mayinclude a thin-film transistor which is manufactured through the samemanufacturing process as that of the first thin-film transistor. Sincethe thin-film transistor connected to the pixel electrode in the imagedisplay area and the thin-film transistor contained in the bottomcircuit are manufactured in the same manufacturing process, themanufacturing process and the laminate structure on the substrate aresimplified. For example, the thin-film transistor is manufactured of asemiconductor layer of amorphous silicon, low-temperature polysilicon,or high-temperature polysilicon.

In a still further embodiment of the third electrooptical device of thepresent invention, an insulator may be formed between the integratedcircuit and the bottom circuit. In accordance with this embodiment, theinsulator formed between the integrated circuit and the bottom circuitreliably isolates one from the other regardless of insulationperformance in the package of the integrated circuit.

In another embodiment of the second and third electrooptical devices ofthe present invention, the integrated circuit may be arranged in aperipheral area surrounding an image display area within which the pixelelectrode is arranged. Since the integrated circuit is arranged in theperipheral area in this embodiment, the image display area isefficiently expanded.

In yet another embodiment of the second and third electrooptical deviceof the present invention, the integrated circuit may be arranged on thesubstrate using the COG (Chip On Glass) method. In accordance with thisembodiment, the surface of the substrate beneath the integrated circuitis fully hidden below the package of the integrated circuit after theintegrated circuit is mounted or glued on the substrate by area, and thepredetermined trace patterns or the bottom circuit is already arranged.A variety of advantages of the predetermined trace patterns and thebottom circuit as discussed above are thus enjoyed.

In yet another embodiment of the second and third electrooptical devicesof the present invention, the top layer of the substrate on which theintegrated circuit is mounted may be planarized.

Although asperities generally exist in any of layers in a laminatestructure in accordance with the predetermined trace patterns and thebottom circuit, the top layer of the substrate is planarized using a CMP(Chemical Mechanical Polishing) process or forming a planarizing layerthrough spin coating in the above embodiment. The integrated circuit isthus easily mounted on the predetermined trace patterns or the bottomcircuit. Even if the integrated circuit is a surface mounting type, suchas a COG type integrated circuit or a flatpack type integrated circuit,the integrated circuit is mounted on a planarized surface without anyproblems.

To resolve the aforementioned problems, a manufacturing method of thepresent invention of manufacturing the second electrooptical device (theembodiments thereof) can include a first formation step for forming apredetermined trace pattern within a predetermined area on thesubstrate, and a test step for performing at least one of the test,evaluation, and monitoring of a manufacturing process in accordance withthe predetermined trace pattern. The method can further include a secondformation step for forming at least the one of the wiring and theelectronic element, and a step of mounting the integrated circuit on thepredetermined area.

In accordance with the manufacturing method of manufacturing the secondelectrooptical device, the predetermined trace patterns can be formedwithin the predetermined area on the substrate, at least one of thetest, evaluation, and monitoring of the manufacturing process isperformed in accordance with the predetermined trace pattern, andsubsequent to or prior to the test, evaluation, and monitoring, thewiring, the electronic element, and the pixel electrodes are formed.Subsequent to these processes, the integrated circuit is mounted on thepredetermined area. Since the test, evaluation, or monitoring of themanufacturing process is completed in accordance with the predeterminedtrace pattern prior to the mounting of the integrated circuit, the samepredetermined area is utilized as an area for the formation of thepredetermined trace pattern and as the mounting area of the integratedcircuit at different timings. This arrangement is very advantageous toefficiently use the limited area of the substrate.

To solve the aforementioned problems, a manufacturing method of thepresent invention of manufacturing the third electrooptical device (andthe embodiments thereof) can include a formation step of forming aperipheral circuit within a predetermined area on the substrate, the oneof the wiring and the electronic element, and the pixel electrode, and astep of mounting the integrated circuit on the predetermined area.

In accordance with the manufacturing method of the third electroopticaldevice of the present invention, the bottom circuit, the wiring, theelectronic element, the pixel electrode, etc. are firstly formed withinthe predetermined area on the substrate. Subsequent to these processes,the integrated circuit is mounted on the predetermined area. The samepredetermined area serves as both the formation area of the bottomcircuit and the mounting area of the integrated circuit, and thisarrangement is very advantageous from the standpoint of efficient use ofthe limited area of the substrate.

In another embodiment of the second electrooptical device of the presentinvention, the predetermined trace pattern may include at least one ofan alignment mark and an identification mark. In accordance with thisembodiment, the predetermined trace pattern can include the alignmentmark used to align the substrate, and the identification mark used toidentify a lot number of the substrate. These marks typically end theusefulness thereof prior to the mounting of the external integratedcircuit in a relatively later phase of the production of theelectrooptical device. Conventionally, even after the electroopticaldevice has been manufactured, however, the marks may remain visible, andthus may unnecessarily occupy an area of the substrate.

In this embodiment, the predetermined trace pattern includes thealignment mark, the identification mark, etc. These marks come under theintegrated circuit. With the integrated circuit overlapping these marks,the area occupied by the marks and the integrated circuit can benarrowed accordingly. As already discussed, the alignment mark, theidentification mark, etc. no longer necessary are only covered with theintegrated circuit, substantially with no problems. Accordingly, thisarrangement allows the image display area having the pixel electrodesarranged therewithin to be relatively expanded in the limited area ofthe substrate.

In another embodiment of the third electrooptical device of the presentinvention, the bottom circuit may include a circuit element, and theelectrooptical device may include a lead wiring extending from thecircuit element, and an external circuit connection terminal for thebottom circuit connected to the lead wiring in a portion of thesubstrate not facing the integrated circuit. In accordance with thisembodiment, the bottom circuit containing the test circuit, for example,includes circuit elements such as a thin-film transistor and a thin-filmdiode, and a lead wiring and an external circuit connection terminal forthe bottom circuit are connected to the circuit elements. Thus in thisembodiment, even after the integrated circuit is mounted on thesubstrate, the bottom circuit of the substrate and the circuit elementscontained in the bottom circuit are used. For example, when the bottomcircuit is a TEG (Test Element Group) or the test circuit, the testingmay be carried out on the electrooptical device even after theintegrated circuit is mounted.

To resolve the aforementioned problems, a fourth electrooptical deviceof the present invention includes a substrate, a peripheral circuitembedded in the substrate, a first wiring arranged on the substrate, anintegrated circuit including a first terminal connected to aninterconnection portion arranged on the first wiring on the substrate, asecond wiring which extends from the interconnection portion in such amanner that the second wiring is routed in a portion of the substratefacing the integrated circuit, and a first external circuit connectionterminal arranged on the second wiring in a portion of the substrate notfacing the integrated circuit. The electrooptical device can furtherinclude, on the substrate, a pixel electrode, and at least one of awiring and an electronic element for driving the pixel electrode. Theintegrated circuit, mounted on the substrate, forms at least a portionof a driving circuit connected to at least the one of the wiring and theelectronic element. A predetermined trace pattern or a bottom circuit isarranged beneath the integrated circuit.

The fourth electrooptical device of the present invention can include acombination of the requirements of the first electrooptical device andthe requirements of the second or third electrooptical device. Thepresent invention thus provides the aforementioned advantages of thefirst electrooptical device that the electrical test is performedwithout the need for detaching the integrated circuit and the advantagesof the peripheral circuit and the advantages of the integrated circuit.Furthermore, the present invention provides the advantages of the secondor third electrooptical device that the predetermined trace pattern orthe bottom circuit is arranged beneath the integrated circuit.Therefore, as the integrated circuit overlaps the predetermined tracepattern or the bottom circuit, the area occupied by the predeterminedtrace pattern or the bottom circuit can be narrowed accordingly in thearea of the substrate. The image display area within which the pixelelectrodes are arranged becomes relatively large in the limited area ofthe substrate.

If the requirements of the first, second, and third electroopticaldevices of the present invention are combined, the above-referencedadvantages are concurrently provided. Furthermore, thin and compactdesigns are implemented, while the image display area is expanded. Anelectrooptical device that satisfies two mutually contradictoryrequirements of a compact design and a large screen results.

In this specification, the peripheral circuit can be included in thebottom circuit, and vice versa.

To resolve the aforementioned problems, electronic equipment of thepresent invention can include the first electrooptical device (and theembodiments thereof), or the second or third electrooptical device ofthe present invention (and the embodiments thereof), or the fourthelectrooptical device.

The electronic equipment of the present invention including the firstelectrooptical device of the present invention can present ahigh-quality image, and allows the electrical test to be performedwithout the need for detaching the integrated circuit. Such equipmentmay be any of a diversity of electronic equipment including aliquid-crystal display television, a mobile telephone, an electronicpocketbook, a word processor, a viewfinder type or direct monitoringtype video cassette recorder, a workstation, a video phone, a POSterminal, a touch panel, a projection-type display apparatus, and thelike.

The electronic equipment of the present invention including the secondor third electrooptical device of the present invention provides animage display area relatively wide with respect to the size of the bodyof the electronic equipment and implements a compact design. Suchequipment may be any of a diversity of electronic equipment including aliquid-crystal display television, a mobile telephone, an electronicpocketbook, a word processor, a viewfinder type or direct monitoringtype video cassette recorder, a workstation, a video phone, a POSterminal, a touch panel, a projection-type display apparatus, and thelike.

The electronic equipment of the present invention including the fourthelectrooptical device provides the two advantages of the aforementionedelectronic equipment which are simultaneously achieved.

These and other operations and advantages of the present invention willbecome apparent from the following description of the embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with reference to the accompanyingdrawings wherein like numerals reference like elements, and wherein:

FIG. 1 is a perspective view three-dimensionally illustrating a portionof an external IC and its associated components in accordance with thefirst embodiment of the substrate assembly of the present invention;

FIG. 2 is a plan view illustrating a portion of the substrate assemblywhere the external IC is to be mounted in accordance with the firstembodiment of the substrate assembly of the present invention;

FIG. 3 is a plan view illustrating a portion of the substrate assemblywhere the external IC is to be mounted in a comparative substrateassembly;

FIG. 4 is a plan view illustrating a portion of the substrate assemblywhere the external IC is to be mounted in accordance with a modificationof the substrate assembly of the present invention;

FIG. 5 is a plan view illustrating a portion of the substrate assemblywhere the external IC is mounted in accordance with another modificationof the substrate assembly of the present invention;

FIG. 6 is a perspective view three-dimensionally illustrating a portionof an external IC and its associated components in accordance with thesecond embodiment of the substrate assembly of the present invention;

FIG. 7 is a plan view of a portion of the substrate assembly where theexternal IC is to be mounted in accordance with the second embodiment ofthe substrate assembly of the present invention;

FIG. 8 is a cross-sectional view of the substrate assembly taken alongline C1-C1′ in FIG.7;

FIG. 9 is a process diagram illustrating manufacturing steps in a crosssection taken along line D-D′ in FIG. 7;

FIG. 10 is a cross-sectional view of a modification of the substrateassembly taken along line C1-C1′ in FIG. 7;

FIG. 11 is a perspective view three-dimensionally illustrating a portionof an external IC and its associated components in accordance with thethird embodiment of the substrate assembly of the present invention;

FIG. 12 is a plan view of a portion of the substrate assembly where theexternal IC is to be mounted in accordance with the third embodiment ofthe substrate assembly of the present invention;

FIG. 13 is a cross-sectional view of the substrate assembly taken alongline C2-C2′ in FIG. 12;

FIG. 14 is a plan view of the TFT array substrate with componentsmounted thereon, in the electrooptical device of the embodiment of thepresent invention viewed from the counter substrate;

FIG. 15 is a cross-sectional view of the TFT array substrate taken alongline H-H′ in FIG. 14;

FIG. 16 is an equivalent circuit diagram of a variety of devices in amatrix of pixels forming the image display area of the electroopticaldevice, and wirings in the electrooptical device of the embodiment ofthe present invention;

FIG. 17 is a plan view illustrating a plurality of pixels adjacent toeach other in the TFT array substrate in the electrooptical device ofthe embodiment having the data lines, the scanning lines, and the pixelelectrodes formed thereof;

FIG. 18 is a cross-sectional view of the substrate assembly taken alongline A-A′ in FIG. 17; and

FIG. 19 is a cross-sectional view of a color liquid-crystal projector asone example of projection type color display device in the embodiment ofthe electronic equipment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A first embodiment of the substrate assembly of the present inventionwill be discussed with reference to FIG. 1 through FIG. 5. FIG. 1 is athree-dimensional, exploded perspective view of an external IC and thesurrounding portion thereof in the first embodiment of the substrateassembly of the present invention, FIG. 2 is a plan view of thesubstrate assembly in and near the mounting area of the external IC,FIG. 3 is a plan view of the substrate assembly in and near the mountingarea of the external IC in a comparative substrate assembly. FIG. 4 is aplan view of the substrate assembly in and near the mounting area of theexternal IC in a modification of the embodiment, and FIG. 5 is a planview of the substrate assembly in and near the mounting area of theexternal IC in another modification of the embodiment.

The substrate assembly of the first embodiment is preferably used as aTFT array substrate having a peripheral circuit and a COG type IC in aliquid-crystal device in one example of an electrooptical device to bedescribed later. Specifically, the substrate assembly of the firstembodiment includes a COG type IC as an external IC, and a drivingcircuit of the liquid-crystal device is formed of the COG type IC andthe peripheral circuit.

Referring to FIG. 1 and FIG. 2, the substrate assembly 200A of the firstembodiment can include a TFT array substrate 10, a scanning line drivingcircuit 104 and a sampling circuit 118 embedded in the TFT arraysubstrate 10 as one example of a peripheral circuit, first wirings 201,second wirings 202, and third wirings 203 arranged on the TFT arraysubstrate 10, and a data line driving circuit 101 arranged on the TFTarray substrate 10 and formed of a COG type IC as one example of anexternal IC.

The scanning line driving circuit 104 is a driving circuit for drivingan unshown scanning line arranged in an image display area 10 a. Thesampling circuit 118, including sampling switches, samples a videosignal on an video signal line (not shown), and feeds the sampled videosignal to unshown data lines arranged within the image display area 10a. The data line driving circuit 101 is formed of a COG type IC havingoutput terminals 221 as first terminals, and input terminals 222 assecond terminals. The scanning line driving circuit 104 and the samplingcircuit 118, as one example of the peripheral circuit, includeshigh-temperature polysilicon TFTs or low-temperature polysilicon TFTswhich are manufactured in the same manufacturing process as that ofpixel switching TFTs which are embedded into the image display area 10 aas will be described later.

The scanning line driving circuit 104, the sampling circuit 118, thedata line driving circuit 101, and the image display area 10 a will bedescribed in detail below in the discussion of the embodiments of theelectrooptical device.

The output terminal 221 of the data line driving circuit 101 isconnected to an interconnection pad 211 as an interconnection portionarranged on the first wiring 201 within an area 101S (a rectangular areaoutlined by a broken line as shown in FIG. 2) on which the data linedriving circuit 101 is mounted in the TFT array substrate 10. The inputterminal 222 of the data line driving circuit 101 is connected to aninterconnection pad 212 as one example of another interconnectionportion arranged on the third wiring 203 within the area 101S on whichthe data line driving circuit 101 is mounted in the TFT array substrate10.

The first wiring 201 extends from the interconnection pad 211 beyond thearea 101S of the TFT array substrate 10, and thus reaches the samplingcircuit 118.

The second wiring 202 extends from the interconnection pad 211 beyondthe area 101S of the TFT array substrate 10 and reaches a first externalcircuit connection terminal 102 a arranged along the edge of thesubstrate 10.

The third wiring 203 extends from the interconnection pad 212 beyond thearea 101S of the TFT array substrate 10 and reaches a second externalcircuit connection terminal 102 b arranged along the edge of thesubstrate 10.

In the first embodiment, external circuit connection terminals 102including the first external circuit connection terminal 102 a and thesecond external circuit connection terminal 102 b are arranged along theedge of the TFT array substrate 10. The external circuit connectionterminals 102 are positioned clear of the area 101S on the TFT arraysubstrate 10.

The test method of the substrate assembly 200A thus constructed isdescribed below.

Before mounting the data line driving circuit 101 formed of the COG typeIC, the scanning line driving circuit 104 and the sampling circuit 118,as the peripheral circuit, and the data line, the scanning line, thepixel switching TFT, the capacitive line, and a storage capacitormounted within the image display area 10 a are electrically testedthrough the first external circuit connection terminal 102 a and thesecond external circuit connection terminal 102 b.

Then, after mounting the data line driving circuit 101 formed of the COGtype IC, or after completing the manufacture of the substrate assembly200A or the electrooptical device containing the substrate assembly200A, or at a fault or malfunction of the substrate assembly 200A or theelectrooptical device after the shipment thereof, a test probe isbrought into contact with the first external circuit connection terminal102 a. Through the test probe, an electrical test is conducted on thedata line driving circuit 101 as the external IC. Specifically, besidesbasic electrical continuity test and insulation test, a variety of testscan be performed. For example, a diversity of input signals such as avideo signal, a control signal, and a power source signal can be inputto the second external circuit connection terminals 102 b connected theinput terminals 222 of the data line driving circuit 101, and outputsignals that can be continuously output from the first external circuitconnection terminals 102 a connected to the output terminals 221 of thedata line driving circuit 101 can be compared with the output signals tobe normally obtained.

When the second wiring 202 and the first external circuit connectionterminal 102 a are not used in the arrangement of the first embodimentwith reference to the comparative substrate assembly in FIG. 3, theoutput of the data line driving circuit 101 cannot be tested once thedata line driving circuit 101 as the external IC is mounted on the TFTarray substrate 10, or the output may be tested with the data linedriving circuit 101 detached from the TFT array substrate 10. When anyfault is found, it is impossible to determine which one of theperipheral circuit composed of the scanning line driving circuit, thesampling circuit and the external IC is faulty.

As described above, in the substrate assembly 200A of the firstembodiment, a portion of the function required of a circuit on the TFTarray substrate 10 is shouldered by the peripheral circuit composed ofthe sampling circuit 118 and the scanning line driving circuit 104, andthe other portion of the function required of the circuit on the TFTarray substrate 10 is shouldered by the data line driving circuit 101 asthe separate IC. When the device is faulty or malfunctions, an externaltest instrument may test the output signal of the data line drivingcircuit 101 as the separate IC through the first external circuitconnection terminal 102 a without the need for detaching the data linedriving circuit 101 from the TFT array substrate 10.

In the first embodiment, the data line driving circuit 101 is formed ofthe COG type IC. After the mounting of the data line driving circuit101, the output terminal 221 and the input terminal 222 arranged on themounting surface of the COG type IC are hidden below the package body ofthe COG type IC. However, the output signals of the COG type IC formingthe data line driving circuit 101 and the peripheral circuit are testedfrom outside through the first external circuit connection terminal 102a without any problems.

Rather than in the COG type IC, the data line driving circuit 101 may beformed in any of a variety of packages, such as a DIP package, aflatpack package, a chip carrier package, and may be mounted on the TFTarray substrate 10 using any of a wire bonding method, a flipchipmethod, and a beam lead method. In any case, the data line drivingcircuit 101 and the peripheral circuit are relatively easily testedthrough the first external circuit connection terminal 102 a even afterthe data line driving circuit 101 is mounted.

In the first embodiment, in particular, instead of the peripheralcircuit composed of the sampling circuit 118 and the scanning linedriving circuit 104, a sampling circuit 118 and a scanning line drivingcircuit 104 may be mounted as a separate IC. In this arrangement, thefunction of the driving circuit required of the TFT array substrate 10is split between two separate ICs, and the flexibility of design isincreased. The TFT array substrate 10 may be a glass substrate, a quartzsubstrate, or a tape substrate, and the external IC may be mounted usinga TAB (Tape Automated Bonding). This arrangement still provides theadvantage that the data line driving circuit 101 is tested from outsidethrough the first external circuit connection terminal 102 a without theneed for detaching the data line driving circuit 101 formed of an ICexternal to the substrate assembly.

In the first embodiment, a plurality of output terminals 221 and aplurality of input terminals 222 of the COG type IC forming the dataline driving circuit 101 are arranged in a zigzag fashion within themounting surface of the COG type IC. As seen from FIG. 1 and FIG. 2, thesecond wirings 202 and the third wirings 203, respectively, linearlyextend from the interconnection pads 211 and 212 which respectivelycorrespond to the output terminals 221 and the input terminals 222. Thesecond wiring 202 alternates with the third wiring 203, and the firstexternal circuit connection terminal 102 a alternates with the secondexternal circuit connection terminal 102 b. This arrangement efficientlyprevents the wirings from overlapping one next to the other side by sidewhile also preventing the external circuit connection terminals fromoverlapping one next to the other side by side.

With reference to a modification illustrated in FIG. 4, a plurality ofoutput terminals 221 may be respectively in alignment with a pluralityof input terminals 222, in the COG type IC forming the data line drivingcircuit 101. In this case, the interconnection pads 211′ are alsorespectively in alignment with the interconnection pad 212′, and eachsecond wiring 202′ extending from the corresponding interconnection pad211′ is routed in a trace pattern that evades the interconnection pad212′ and the third wiring 203.

With reference to a modification illustrated in FIG. 5, first externalcircuit connection terminals 102 a′ and second external circuitconnection terminals 102 b′ may be alternately aligned in a line alongthe edge of the TFT array substrate 10. As long as the pitch of thefirst external circuit connection terminals 102 a′ and the secondexternal circuit connection terminals 102 b′ is sufficiently large,these terminals are aligned in a line so that the connection of anexternal circuit to these terminals is easily established.

A second embodiment of the substrate assembly of the present inventionis discussed below with reference to FIG. 6 through FIG. 9. FIG. 6 is anexploded perspective view three-dimensionally illustrating an externalIC and the associated components thereof in the second embodiment of thesubstrate assembly, FIG. 7 is a plan view partially illustrating thearea of the substrate assembly where the external IC is mounted, FIG. 8is a cross-sectional view of the substrate assembly taken along lineC1-C1′ in FIG. 6, and FIG. 9 is a process diagram illustrating themanufacturing process of the substrate assembly in a cross section D-D′in FIG. 6.

With reference to FIG. 6 through FIG. 8, and a manufacturing step (4) inFIG. 9, the substrate assembly 200B of the second embodiment can includea TFT array substrate 10. A scanning line driving circuit 104 and asampling circuit 118 are embedded as one example of the peripheralcircuit in the TFT array substrate 10. An interconnection pad 211 isattached to the end of each sampling-circuit driving signal line 114arranged on the TFT array substrate 10 within an area 101S (see FIG. 7)on which the data line driving circuit 101 is mounted. Within the area101S on which the data line driving circuit 101 is mounted, aninterconnection pad 212 is attached to the end of each third wiring 203extending from an external circuit connection terminal 102.

The data line driving circuit 101 mounted on the TFT array substrate 10is formed of an COG type IC having output terminals 221 and inputterminals 222. The data line driving circuit 101 is then mounted withinthe area 101S in such a manner that the output terminals 221 arerespectively connected to the interconnection pads 211 and that theinput terminals 222 are respectively connected to the interconnectionpads 212.

Each of the scanning line driving circuit 104 and the sampling circuit118 includes high-temperature polysilicon TFTs or low-temperaturepolysilicon TFTs manufactured in the same manufacturing process as thatof pixel switching TFTs which are embedded in the image display area 10a as will be described below. The scanning line driving circuit 104 andthe sampling circuit 118 are thus embedded in the TFT array substrate 10as a peripheral circuit.

In accordance with the second embodiment, trace patterns 230 fortesting, evaluating, and monitoring the manufacturing process or forevaluating elements are formed and come beneath the data line drivingcircuit 101. The trace patterns 230 are arranged to be optically orvisibly read. Using the trace patterns 230, the manufacturing process isevaluated, tested, or monitored or the element is evaluated until amanufacturing step immediately prior to a manufacturing step of mountingthe data line driving circuit 101. In the second embodiment, the tracepatterns 230 are no longer used after the data line driving circuit 101is mounted. Referring to FIG. 6 and FIG. 7, accordingly, the tracepatterns 230 are formed within a major portion of the area 101S on whichthe data line driving circuit 101 is mounted. Specifically, although thetrace patterns 230 are hidden beneath the package body of the data linedriving circuit 101, no problem is presented, because the trace patterns230 have already finished the function thereof for evaluating, testing,and monitoring the manufacturing process or for evaluating the element.

In accordance with the second embodiment, the data line driving circuit101 overlaps the trace patterns 230 so that the area occupied by thesetwo components is narrowed accordingly. In this arrangement, thus, theperipheral area of the TFT array substrate 10 is narrowed while theimage display area 10 a is relatively expanded. A compact electroopticaldevice with a large screen thus results.

In the second embodiment, referring to FIG. 8 and the manufacturing step(4) in FIG. 9, an underlayer insulator 12, a first interlayer insulator41, a second interlayer insulator 42, and a third interlayer insulator43 are laminated below the data line driving circuit 101 as in aninterlayer insulator structure in an image display area to be discussedlater. Furthermore, the trace patterns 230 are fabricated of islandssandwiched between interlayer insulators, and these conductive filmssandwiched between the interlayer insulators form the sampling-circuitdriving signal line 114 and the wiring 203. The pattern and the wiringare preferably formed of the same film as the conductive film formingthe wiring and the TFT within the image display area. In thisarrangement, the manufacturing process and the laminate structure in theTFT array substrate 10 are simplified.

Referring to FIG. 8 and the manufacturing step (4) in FIG. 9, the tracepatterns 230 are formed between the TFT array substrate 10 and theunderlayer insulator 12. However, it should be understood that the tracepatterns 230 are set at any laminar position. For example, the tracepatterns 230 may be set between the first interlayer insulator 41 andthe second interlayer insulator 42, or between the second interlayerinsulator 42 and the third interlayer insulator 43 depending on thepurpose of the trace patterns 230, such as for testing, evaluating, andmonitoring the manufacturing process or for evaluating the element.

With reference to FIG. 8 and the manufacturing step (4) in FIG. 9, inthe second embodiment, the top surface of the third interlayer insulator43 serving as the mounting surface of the data line driving circuit 101formed of the COG type IC is planarized by forming a planarized layerthrough a CMP process or a spin coating process. Even with the data linedriving circuit 101 mounted by area on the trace patterns 230,accordingly, the data line driving circuit 101 is free from the surfaceirregularity of the mounting surface, and remains stable.

The manufacturing method of the electrooptical device of the secondembodiment thus constructed is discussed with reference to FIG. 9.

An insulator substrate such as a glass substrate or a quartz substrateis prepared as the TFT array substrate 10 in a manufacturing step (1) inFIG. 9.

In a manufacturing step (2), the trace patterns 230 are formed on theTFT array substrate 10. For example, the trace patterns 230 are producedby forming a refractory metal layer through a sputtering process, andthen by patterning the refractory metal layer through photolithographicand etching processes. The underlayer insulator 12 is then deposited onthe trace patterns 230.

In a manufacturing step (3), a data line 6 a, a scanning line 3 a, a TFT30, etc. having the following structure are produced from a variety ofsemiconductor layers and electrically conductive layers within the imagedisplay area. To isolate one layer from another, the first interlayerinsulator 41, the second interlayer insulator 42, and the thirdinterlayer insulator 43 are successively deposited. The third interlayerinsulator 43 is then planarized by the CMP process. Alternatively, thethird interlayer insulator 43 can be planarized by a spin coatingprocess.

In the manufacturing steps (2) and (3) in the second embodiment, thetrace patterns 230 are used to test, evaluate, and monitor the data line6 a, the scanning line 3 a, and the TFT 30 having the structuredescribed below in terms of the position and spacing thereof when theseelements are formed. The trace patterns 230 are used to test, evaluate,and monitor a variation in the thickness of each electrically conductivelayer and each insulator layer, or to evaluate an element forming theimage display area or a peripheral circuit.

In the manufacturing step (4), the data line driving circuit 101 ismounted within the area 101S subsequent to the test, evaluation, andmonitoring of the manufacturing process and the evaluation of theelement through the trace patterns 230.

Through the manufacturing process, the area 101S on which the data linedriving circuit 101 is mounted serves as an area on which the tracepatterns 230 are formed at one time and serves as an area on which thedata line driving circuit 101 is mounted at the other time.

As discussed above, in the electrooptical device of the secondembodiment, one portion of the function required of the circuit of theTFT array substrate 10 is shouldered by the sampling circuit 118 and thescanning line driving circuit 104 as the peripheral circuit, and theother portion of the function of the circuit of the TFT array substrate10 is shouldered by the data line driving circuit 101 as the externalIC. The area 101S on which the data line driving circuit 101 is alsoused as the formation area of the trace patterns 230. The limited areaof the substrate is efficiently used, and the image display area is thusexpanded.

A modification of the second embodiment is discussed with reference toFIG. 10. FIG. 10 is a cross-sectional view of the substrate assemblytaken along line C1-C1′ in FIG. 7.

Referring to FIG. 10, a peripheral circuit 250 including a TFT 240,instead of the trace patterns 230, is produced beneath the data linedriving circuit 101 formed of a COG type IC. The TFT 240 includes asemiconductor layer 241, a gate insulator 242, a gate electrode 243, asource electrode 244, and a drain electrode 245. The TFT 240 ispreferably fabricated of the same layer as that of the TFT 30 in thesame manufacturing process as that of the TFT 30 in the image displayarea 10 a. The peripheral circuit 250 may be a portion of a drivingcircuit, such as the sampling circuit 118 or the scanning line drivingcircuit 104, or may be a test circuit. The rest of the construction ofthe modification remains unchanged from that of the second embodiment.

In accordance with this modification, the data line driving circuit 101manufactured as an external IC outperforms, in switching performance andlow power consumption feature, the data line driving circuit 101 whichis formed of the peripheral circuit that can be embedded in the samemanufacturing process as that of the TFT 30 in the image display area 10a with the low-temperature polysilicon or the high-temperaturepolysilicon used as the semiconductor layer. Arranged below the dataline driving circuit 101 is the peripheral circuit 250, such as aportion of the driving circuit or the test circuit, modestly excellentin switching performance and power consumption. The driving circuit andthe peripheral circuit, each having efficient and high overallperformance, can be produced on the TFT array substrate 10. The imagedisplay area 10 a can be also relatively expanded.

The peripheral circuit 250 may be formed in an area other than the areasof the interconnection pads 211, the interconnection pad 212, the thirdwirings 203, and the sampling-circuit driving signal lines 114.Alternatively, the peripheral circuit 250 may at least underlap any ofthe interconnection pad and the wiring with an insulator layer arrangedtherebetween.

The peripheral circuit 250 may be a dedicated test circuit for testingthe manufacturing process prior to the mounting of the data line drivingcircuit 101, or may be a dedicated test circuit for testing themanufacturing process regardless of whether it is before or after themounting of the data line driving circuit 101.

In the above second embodiment and the modification thereof, rather thanin the COG type IC, the data line driving circuit 101 may be formed inany of a variety of packages, such as a DIP package, a flatpack package,a chip carrier package, and the like. Further, the data line drivingcircuit 101 may be mounted on the TFT array substrate 10 using any of awire bonding method, a flipchip method, and a beam lead method. In anycase, space saving is promoted by placing the trace patterns 230 or theperipheral circuit 250 on the same area as that of the data line drivingcircuit 101.

In the second embodiment and the modification thereof, instead of theperipheral circuit composed of the sampling circuit 118 and the scanningline driving circuit 104, a sampling circuit 118 and a scanning linedriving circuit 104 may be mounted as a separate IC. In thisarrangement, the function of the driving circuit required of the TFTarray substrate 10 is split between two separate ICs, and theflexibility of design is increased. The TFT array substrate 10 may be aglass substrate, a quartz substrate, or a tape substrate, and theexternal IC may be mounted using a TAB (Tape Automated Bonding). Thisarrangement still provides the advantage that space saving is promotedby placing the trace patterns 230 or the peripheral circuit 250 on thesame area as that of the data line driving circuit 101.

A third embodiment of the substrate assembly of the present invention isdiscussed with reference to FIG. 11 through FIG. 13. FIG. 11 is anexploded perspective view three-dimensionally illustrating an externalIC and the associated components thereof in the third embodiment of thesubstrate assembly of the present invention, FIG. 12 is a plan viewpartially illustrating the area of the substrate assembly where theexternal IC is mounted, and FIG. 13 is a cross-sectional view of thesubstrate assembly taken along line C2-C2′ in FIG. 12.

The third embodiment is an application of the TFT array substrate 10 ineach of the first and second embodiments. The third embodiment issimilar in construction to each of the first and second embodiments.Elements in FIG. 11 through FIG. 13 identical to those described withreference up to FIG. 10 are designated with the same reference numerals,and the discussion thereof is only briefly made or omitted. In otherwords, the third embodiment will be discussed focussing on theconstruction unique thereto.

A substrate assembly 200C of the third embodiment includes a TFT arraysubstrate 10 as illustrated in FIG. 11 through FIG. 13. A peripheralcircuit 250 including a TFT 240 is arranged on the TFT array substrate10 within an area 101S on which the data line driving circuit 101 ismounted and below the data line driving circuit 101. The TFT 240includes a semiconductor layer 241, a gate insulator 242, a gateelectrode 243, a source electrode 244, and a drain electrode 245. TheTFT 240 is preferably fabricated of the same layer as that of the TFT 30in the same manufacturing process as that of the TFT 30 in the TFT arraysubstrate 10 a.

As in the second embodiment, the data line driving circuit 101manufactured as an external IC in the third embodiment outperforms, inswitching performance and low power consumption feature, the data linedriving circuit 101 which is formed of the peripheral circuit that isembedded in the same manufacturing process as that of the TFT 30 in theimage display area 10 a with the low-temperature polysilicon or thehigh-temperature polysilicon used as the semiconductor layer. Arrangedbelow the data line driving circuit 101 is the peripheral circuit 250,such as a portion of the driving circuit or the test circuit, modestlyexcellent in switching performance and power consumption. The drivingcircuit and the peripheral circuit, each having efficient and highoverall performance, are produced on the TFT array substrate 10. Theimage display area 10 a is also relatively expanded.

In the third embodiment, ends of lead lines 900 are respectivelyconnected to the gate electrode 242, the source electrode 244, and thedrain electrode 245 forming the TFT 240. TFT terminals 902, 904, and906, as example of external circuit connection terminals for the bottomcircuit stated in the discussion of the present invention, are formed onthe TFT array substrate 10 in a way similar to the way in which theexternal circuit connection terminals 102 are arranged in the substrateassembly 200A in the first embodiment. The other ends of the lead lines900 are respectively connected to the TFT terminals 902, 904, and 906.

In the substrate assembly 200C of the third embodiment, the TFT 240 isembedded below the data line driving circuit 101 while the gateelectrode 242, the source electrode 244, and the drain electrode 245 ofthe TFT 240 are respectively controlled from outside through the TFTterminals 902, 904, and 906. In accordance with the third embodiment,the TFT 240 is effectively used even after the data line driving circuit101 is mounted. For example, when the TFT 240 forms a portion of a testcircuit, the operation test of the substrate assembly 200C or theperipheral circuit 250 may be carried out during maintenance in themiddle of use after the shipment.

In accordance with the third embodiment, the above-mentioned lead linesand the external circuit connection terminals for the bottom circuit arearranged for circuit elements, such as the TFT 240 contained in theperipheral circuit 250. The workload on the substrate assembly 200C isflexibly shared between the data line driving circuit 101 as theexternal IC and the peripheral circuit 250, and the flexibility ofdesign of the substrate assembly is heightened.

The construction of the third embodiment has been discussed by way ofexample only. For example, the lead lines are connected to allelectrodes of the TFT 240, and the TFT terminals 902, 904, and 906 arerespectively connected to these lead lines. However, it should beunderstood that the present invention is not limited to this embodiment.The lead lines and the external circuit connection terminals for thebottom circuit are arranged for only the electrodes which need to becontrolled from outside. Broadly, the circuit element the lead line isconnected to is not limited to the TFT. The circuit element may be athin-film diode, a capacitor, or other element without departing fromthe spirit and scope of the present invention.

The first, second, and third embodiments have been discussed focusing onthe respective features thereof. However, it should be understood thatthe present invention is not limited to these specific embodiments. Anelectrooptical device having the features of the first and secondembodiments in combination, an electrooptical device having the featuresof the second and third embodiments in combination, and anelectrooptical device having the features of the first and thirdembodiments in combination fall within the scope of the presentinvention. An electrooptical device having all features of the first,second, and third embodiments also falls within the scope of the presentinvention.

One embodiment of the electrooptical device of the present invention isdiscussed with reference to FIG. 14 through FIG. 18. The electroopticaldevice of this embodiment is a liquid-crystal device having theaforementioned substrate assembly 200 on a TFT array substrate.

The general construction of the electrooptical device of this embodimentis discussed with reference to FIG. 14 and FIG. 15. Discussed here as anexample of the electrooptical device is a TFT active matrixliquid-crystal device having a built-in driving circuit. FIG. 14 is aplan view of the TFT array substrate with components mounted thereon,viewed from a counter substrate, and FIG. 15 is a cross-sectional viewof the TFT array substrate taken along line H-H′ in FIG. 14.

Referring to FIG. 14 and FIG. 15, the electrooptical device of thisembodiment includes a TFT array substrate 10 and a counter substrate 20.A liquid-crystal layer 50 is encapsulated between the TFT arraysubstrate 10 and the counter substrate 20, and the TFT array substrate10 and the counter substrate 20 are bonded to each other with a sealingmember 52 arranged in a sealing area surrounding an image display area10 a. To bond the two substrates, the sealing member 52 may befabricated of a thermosetting resin, a photo-thermo-setting resin, aphoto-setting resin, an ultraviolet curing resin, or the like, and isapplied on the TFT array substrate 10 during the manufacturing process,and is then set by a heating, a heating and light irradiation process, alight irradiation process, an ultraviolet irradiation process, or thelike.

A gap material, such as of glassfiber or glass beads, is contained inthe sealing member 52 to keep the spacing between the two substrates (asubstrate gap) to a predetermined value. The electrooptical device ofthis embodiment is appropriate for use as a light valve for a projectorwhich is compact and displays an expanded image. If the electroopticaldevice is a liquid-crystal device, such as a liquid-crystal display or aliquid-crystal television, which is large and presents unmagnifiedimages, such a gap material may be contained in the liquid-crystal layer50.

Intersubstrate connection materials 106, arranged at the four corners ofthe counter substrate 20, establish electrical connection betweenintersubstrate connection terminals arranged on the TFT array substrate10 and a substrate electrode 21 of the counter substrate 20.

Referring to FIGS. 14 and 15, a light-shield frame outline 53, definingthe image display area 10 a and arranged inside and along the sealingarea of the sealing member 52, is mounted on the counter substrate 20.Alternatively, the light-shield frame outline 53 may be mounted on theTFT array substrate 10. The data line driving circuit 101 and theexternal circuit connection terminals 102 are arranged along one side ofthe TFT array substrate 10, on an exterior portion outside the sealingarea of the sealing member 52 in the peripheral area surrounding theimage display area, and the scanning line driving circuits 104 arearranged along two sides of the TFT array substrate 10 perpendicular tothe one side. A plurality of wirings 105 for connecting the scanningline driving circuits 104 arranged on both sides of the image displayarea 10 a are arranged on the remaining one side of the TFT arraysubstrate 10.

Referring to FIG. 15, the TFT array substrate 10 includes an alignmentlayer which is formed on pixel electrodes 9 a on which the scanninglines for switching pixel TFTs and the wirings for the data lines havebeen formed. The counter substrate 20 includes the counter electrode 21and an alignment layer as a top layer thereof. The liquid-crystal layer50 is a liquid crystal formed of one or several types of nematic liquidcrystals in combination, and takes a predetermined alignment statebetween the pair of alignment layers.

In this embodiment, the sampling circuit 118 is arranged beneath thelight-shield frame outline 53 on the TFT array substrate 10. In responseto a sampling-circuit driving signal supplied from the data line drivingcircuit 101, the sampling circuit 118 samples a video signal on a videosignal line and feeds the sampled video signal to the data line.

In this embodiment, the data line driving circuit 101 is formed of theCOG type IC, and is attached to the TFT array substrate 10. In contrast,the scanning line driving circuit 104 and the sampling circuit 118 areembedded in the TFT array substrate 10, and contain the TFTs which aremanufactured in the same manufacturing process as that of the pixelswitching TFTs, one arranged for each pixel within the image displayarea as will be discussed in greater detail below.

The circuit arrangement and operation of the electrooptical device thusconstructed are discussed with reference to FIG. 16. FIG. 16 is a blockdiagram of an equivalent circuit diagram of a variety of elements in amatrix of pixels forming the image display area of the electroopticaldevice, wirings, and a peripheral circuit.

Referring to FIG. 16, the pixel electrode 9 a and the TFT 30 forswitching-controlling the pixel electrode 9 a are formed in each of thepixels in a matrix forming the image display area of the electroopticaldevice of this embodiment, and the data line 6 a supplied with the videosignal is electrically connected to the source of the TFT 30.

One end of the data line 6 a (the lower end thereof in FIG. 16) isconnected to the drain of each switching device, such as a TFT in thesampling circuit 118, within the peripheral area surrounding the imagedisplay area 10 a. A video signal line 115 is connected the source ofthe TFT in the sampling circuit 118 through a lead line 116. Thesampling-circuit driving signal line 114 connected to the data linedriving circuit 101 is connected to the gate of the TFT in the samplingcircuit 118. The sampling circuit 118 samples video signals S1, S2, . .. , Sn on the video signal lines 115 and feeds the sampled video signalsS1, S2, . . . , Sn to the data lines 6 a in response to the samplingcircuit driving signals supplied through the sampling circuit drivingsignal line 114 from the data line driving circuit 101.

The video signals S1, S2, . . . , Sn to be written on the data lines 6 amay be supplied in that order, or may be supplied to a group of adjacentlines 6 a at a time.

Scanning lines 3 a are respectively electrically connected to the gatesof the TFTs 30 and are supplied with scanning signal G1, G2, . . . , Gmin the form of pulse at a predetermined timing in a one-line-at-a-timemanner in that order by the scanning line driving circuit 104. Pixelelectrodes 9 a are respectively electrically connected to the drains ofthe TFTs 30, and the video signals S1, S2, . . . , Sn fed through thedata lines 6 a are written at a predetermined timing by closing the TFTs30, as a switching element, for a predetermined duration of time. Thevideo signals S1, S2, . . . , Sn at a predetermined level, which arewritten on a liquid crystal through the pixel electrodes 9 a, are storedin the liquid crystal as one example of the electrooptical device withthe counter electrode 21 formed on the counter substrate for apredetermined duration of time. The liquid crystal modulates light topresent it in a gradation by varying the orientation or the order of thecollection of molecules. In a normally white mode, light transmittanceto incident light is reduced depending on a voltage applied on eachpixel, while in a normally black mode, the light transmittance to theincident light is increased depending on a voltage applied on eachpixel, and as a result, the liquid-crystal display device outputs lightbearing a contrast generally responsive to the video signal. To preventthe stored video signal from leaking, a storage capacitor 70 is added inparallel with the capacitor of the liquid crystal formed between thepixel electrode 9 a and the counter electrode 21.

Besides the scanning line driving circuit 104 and the sampling circuit118, the TFT array substrate 10 may be provided with a precharge circuitfor supplying a precharge signal at a predetermined voltage level to theplurality of the data lines 6 a prior to the application of the videosignal, and a test circuit for checking the quality and defects of theelectrooptical device in the middle of the production or at the shipmentthereof.

A variety of these circuits may be embedded as a peripheral circuit ineach of the substrate assemblies 200A, 200B, and 200C respectivelyillustrated in FIG. 1, FIG. 6, and FIG. 11, or may be manufactured as anexternal IC and then may be mounted on each of these substrates.

Specifically, the peripheral circuit, such as the aforementionedprecharge circuit and test circuit, may be embedded in the TFT arraysubstrate 10 in addition to or instead of the scanning line drivingcircuit 104 and the sampling circuit 118. The peripheral circuit such asthe aforementioned precharge circuit and the test circuit may be formedas an external IC in addition to or instead of the data line drivingcircuit 101, and is then attached to the TFT array substrate 10. In thisembodiment, any portion of the driving circuit can be formed as anexternal IC.

Referring to FIG. 17 and FIG. 18, the pixel of the electrooptical devicein this embodiment is discussed. FIG. 17 is a plan view illustrating aplurality of pixels adjacent to each other in the electrooptical devicein which the data lines, the scanning lines, and the pixel electrodesare formed, and FIG. 18 is a cross-sectional view of the electroopticaldevice taken along line A-A′ in FIG. 17. Referring to FIG. 18, layersand members are drawn to different scales for easy identification.

Referring to FIG. 17, the substrate 10 of the liquid-crystal displaydevice includes a matrix of transparent pixel electrodes 9 a (with theoutlines thereof represented by broken lines 9 a′). The data line 6 a,and the scanning line 3 a run respectively vertically and horizontallyalong each pixel electrode 9 a.

The scanning line 3 a is arranged to face the channel region 1 a′, of asemiconductor layer 1 a, represented by a portion hatched withrightwardly upwardly inclined lines. The scanning line 3 a functions asa gate electrode. Arranged at each intersection of the scanning line 3 aand the data line 6 a in this way is a pixel switching TFT 30 having thechannel region 1 a′with the scanning line 3 a serving as the gateelectrode and facing the channel region 1 a′.

In this embodiment, a capacitive line 300 is formed overlapping theformation area of the scanning line 3 a represented by solid lines.Specifically, the capacitive line 300 has a main line portion extendingalong the scanning line 3 a, a projection portion projecting upwardlyalong the data line 6 a from the intersection of the scanning line 3 aand the data line 6 a as shown in FIG. 17, and a narrow portion slightlynarrowed at the area of a contact hole.

Referring to FIG. 17 and FIG. 18, the pixel electrode 9 a iselectrically connected to a heavily doped drain region 1 e of thesemiconductor layer 1 a through contact holes 83 an 85 and a drainelectrode 302 functioning as an electrically conductive extension layerfor interconnection. The data line 6 a is connected to a heavily dopedsource region 1 d through contact holes 81 and 82 and a source electrode303 functioning as an electrically conductive layer for interconnection.

The capacitive line 300 including a fixed-voltage capacitive electrodeis formed on a pixel-voltage capacitive electrode formed of a portion ofthe drain electrode 302 with a dielectric layer 301 sandwiched betweenthe capacitive line 300 and the drain electrode 302. The capacitive line300 can be fabricated of a metal, an alloy, a metal silicide, or apolycide of one selected from the group consisting of Al (aluminum), Ag(silver), Cu (copper), Ti (titanium), Cr (chromium), W (tungsten), Ta(tantalum), Mo (molybdenum), Pb (lead), or is fabricated of a laminateof the metal, a laminate of the alloy, a laminate of the metal silicide,or a laminate of the polycide. In this embodiment, a storage capacitor70 is formed by sandwiching the dielectric layer 301 between a portionof the drain electrode 302 and a portion of the capacitive line 300.

The second interlayer insulator 42, formed on the capacitive line 300,has the contact hole 81 connecting the source electrode 303 to the dataline 6 a and the contact hole 85 connecting the drain electrode 302 tothe pixel electrode 9 a. The second interlayer insulator 42 isfabricated of a silicate glass layer, a silicon nitride layer, or asilicon oxide layer, for example, and has a thickness falling within arange from about 500 to 2000 nm.

The data line 6 a is produced on the second interlayer insulator 42, andthe third interlayer insulator 43 having the contact hole 85 leading tothe drain electrode 302 is deposited on the data line 6 a and the secondinterlayer insulator 42. The data line 6 a, fabricated of alow-resistance metal layer such as Al (aluminum), is produced in apredetermined trace pattern using a sputtering technique, aphotolithographic technique, and an etching technique. The thickness ofthe data line 6 a may be several hundred nm so that sufficientconductivity results in accordance with a line width. On the other hand,the third interlayer insulator 43 can be fabricated of a silicate glasslayer, a silicon nitride layer, or a silicon oxide layer, for example,and the thickness thereof falls within a range of from about 500 to 2000nm.

The pixel electrode 9 a is deposited on top of the third interlayerinsulator 43. The pixel electrode 9 a is fabricated of an electricallyconductive, transparent layer such as an ITO (Indium Tin Oxide) layerusing a sputtering technique, a photolithographic technique, or anetching technique. As in an electrooptical device to be discussed later,an alignment layer subjected to a rubbing process may be used.

The data line 6 a is electrically connected to the heavily doped sourceregion 1 d of the semiconductor layer 1 a through the contact hole 81,the contact hole 82 and through the source electrode 303 as a conductiveextension layer. The pixel electrode 9 a is electrically connected tothe heavily doped drain region 1 e of the semiconductor layer 1 athrough the contact hole 83, the contact hole 85, and through the drainelectrode 302 as a conductive extension layer which is manufactured ofthe same layer as that of the source electrode 303.

Using the drain electrode 302 as the conductive extension layer, even ifan interlayer spacing between the pixel electrode 9 a and thesemiconductor layer 1 a forming the TFT 30 is as long as 1000 nm forexample, the pixel electrode 9 a is connected to the semiconductor layer1 a in an electrically sound fashion through two contact holes 83 and 84having a relatively small diameter and connected in series in a mannerfree from the difficulty of connecting the pixel electrode 9 a to thesemiconductor layer 1 a with a single contact hole. Thus, the apertureratio of the pixel is increased. With the use of such conductiveextension layer, etching through is prevented during the opening of thecontact hole. Similarly, using the source electrode 303, even if aninterlayer spacing between the data line 6 a and the semiconductor layer1 a forming the TFT 30 is long, the data line 6 a is connected to thesemiconductor layer 1 a in an electrically sound fashion through the twocontact holes 81 and 82 having a relatively small diameter and connectedin series in a manner free from the difficulty of connecting the dataline 6 a to the semiconductor layer 1 a with a single contact hole.

Referring to FIG. 17 and FIG. 18, the storage capacitor 70 is formed ofthe drain electrode 302, the capacitive line 300 and the dielectriclayer 301 sandwiched therebetween in an area overlapping the scanningline 3 a and in an area overlapping the data line 6 a in a plan view.

The capacitive line 300 has a generally comb-like configuration,extending to cover the scanning line 3 a and projecting in theprojection thereof to cover the drain electrode 302 within the area ofthe data line 6 a. The drain electrode 302 has a generally L-shapedisland, capacitive electrode, extending in one segment thereof from theintersection of the scanning line 3 a and the data line 6 a, along theprojection of the capacitive line 300 within the area of the data line 6a, and extending in the other segment to near an adjacent data line 6 aalong the capacitive line 300 within the area of the scanning line 3 a.The storage capacitor 70 is thus formed in the area where the L-shapeddrain electrode 302 overlaps the capacitive line 300 with the dielectriclayer 301 sandwiched therebetween.

The drain electrode 302 forming one capacitive electrode of the storagecapacitor 70 is connected to the pixel electrode 9 a through the contacthole 85, while being connected to the heavily doped drain region 1 ethrough the contact hole 83. The drain electrode 302 is thus kept to thepixel electrode voltage.

The capacitive line 300 forming the other electrode of the storagecapacitor 70 extends along an image formation area of the pixelelectrode 9 a, and is electrically connected to a constant-voltage powersource to be at a constant voltage. The constant-voltage power sourcemay be a positive power source or a negative power source which feedspower to the scanning line driving circuit to supply the scanning line 3a with the scanning signal for driving the TFT 30, or to the data linedriving circuit to control the sampling circuit for supplying the dataline 6 a with the video signal, or may be a constant voltage sourcewhich feeds power to the counter substrate.

The dielectric layer 301 of the storage capacitor 70 may be a siliconoxide layer, such as an HTO (High Temperature Oxide) layer or an LTO(Low Temperature Oxide) layer, or a silicon nitride layer, each layerhaving a relatively thin thickness falling within a range from 5 to 200nm. The dielectric layer 301 may be a thermo-oxide layer obtained byoxidizing the surface of the drain electrode 302. To increase thecapacitance of the storage capacitor 70, the thinner the thickness ofthe dielectric layer 301, the better as long as layer reliability isassured.

Referring to FIG. 18, the electrooptical device includes one of thesubstrate assemblies 200A, 200B, and 200C, and the transparent countersubstrate 20 oppositely placed thereto. The counter substrate 20 isfabricated of a glass substrate or a quartz substrate, for instance. TheTFT array substrate 10 is provided with the pixel electrodes 9 a, andarranged on top of them is an alignment layer 16 which has beensubjected to a predetermined alignment process such as a rubbingprocess. The alignment layer 16 is fabricated of an organic thin film,such as a polyimide thin film.

The counter substrate 20 has a counter electrode 21 extending on theentire surface thereof, and an alignment layer 22 therebeneath that hasbeen subjected to a predetermined alignment process such as a rubbingprocess. The counter electrode 21 is fabricated of a transparent,electrically conductive film, such as an ITO film. The alignment layer22 is fabricated of an organic thin film such as a polyimide thin film.

Arranged on the TFT array substrate 10 is a pixel switching TFT 30,adjacent to each pixel electrode 9 a, for controlling the pixelelectrode 9 a.

A light-shield layer may be arranged on the counter substrate 20. Theuse of the light-shield layer controls the entry of incident light beamsfrom the counter substrate 20 to a channel region 1 a′, a lightly dopedsource region 1 b, and a lightly doped drain region 1 c of thesemiconductor layer 1 a of the TFT 30. Furthermore, the light-shieldlayer on the counter substrate may be provided with a highly reflectivesurface for reflecting the incident light beam, thereby preventingtemperature from rising in the electrooptical device.

In this embodiment, the data line 6 a fabricated of aluminum havinglight shield feature may light shield the area along the data line 6 a,out of the light shield area of each pixel, or the capacitive line 300may be fabricated of a light shield layer, thereby light shielding thechannel region 1 a′.

In this arrangement, a liquid crystal is encapsulated in a gapsurrounded by a sealing material between the TFT array substrate 10 andthe counter substrate 20 arranged with the pixel electrodes 9 a facingthe counter electrode 21. A liquid-crystal layer 50 is thus formed. Theliquid-crystal layer 50 takes a predetermined orientation state by thealignment layer 16 and the alignment layer 22 with no electric fieldapplied by the pixel electrode 9 a.

Although the lamination of several electrically conductive layers formssteps on the area along the data line 6 a and the scanning line 3 a inthe embodiment described above, a planarization process may be performedby grooving a trench in the first interlayer insulator 41 and the secondinterlayer insulator 42, and by embedding the wiring of the data line 6a and the TFT 30 in the trench. The steps in the third interlayerinsulator 43 and the second interlayer insulator 42 may be polished awaythrough a CMP process. Alternatively, an organic SOG may be used toplanarize the laminate structure.

In the embodiment described above, the pixel switching TFT 30 preferablyhas the LDD structure shown in FIG. 18. Alternatively, the pixelswitching TFT 30 may have an offset structure in which no impurity ionimplantation is performed on the lightly doped source region 1 b and thelightly doped drain region 1 c, or may have a self-aligned type TFT inwhich a high dose impurity ion is implanted with part of the gateelectrode 3 a being used as a mask, to form heavily doped source anddrain in a self-alignment process. In this embodiment, the gateelectrode of the pixel switching TFT 30 is of a single gate structure inwhich a single gate electrode is interposed between the heavily dopedsource region 1 d and the heavily doped drain region 1 e, butalternatively, more than one gate electrode may be interposedtherebetween. With dual gates or triple gates employed in a TFT, leakagecurrents in junctions between the channel region and the source regionand between the channel region and the drain region are prevented, andthereby a current during off period is reduced. The TFTs forming theperipheral circuit may be produced as one of the variety of TFTs.

Arranged on the light incident side of the counter substrate 20 and thelight exit side of the TFT array substrate 10 in the embodimentsdiscussed with reference to FIG. 14 through FIG. 18 are respectivelypolarizer films, retardation films, and polarizers in predetermineddirections to work with operation modes such as a TN (Twisted Nematic)mode, a VA (Vertically Aligned) mode, or a PDLC (Polymer DispersedLiquid Crystal) mode, and normally white mode/normally black modes.

When the liquid-crystal display of each of the above embodiments isincorporated in a projector, three panels of the electrooptical devicesare used as RGB light valves, and each light valve receives therespective color light separated through RGB color separating dichroicmirrors. In each of the above embodiments, the counter substrate 20 isequipped with no color filter. Optionally, an RGB color filter may bearranged in a predetermined area facing the pixel electrode 9 a havingno light shield layer 23, on the counter substrate 20 along with aprotective film. In this way, the electrooptical device of eachembodiment finds applications in a direct viewing or reflective typecolor electrooptical device, besides the electrooptical projector.Microlenses may be arranged on the counter substrate 20 on a onemicrolens to one pixel basis. A color filter layer may be formed of acolor resist beneath the RGB pixel electrodes 9 a on the TFT arraysubstrate 10. In this way, condensation efficiency of the incident lightis increased, and an electrooptical device providing a bright imageresults. By laminating interference layers having different refractiveindexes on the counter substrate 20, a dichroic filter for creating theRGB colors is formed taking advantage of interference of light. Thecounter substrate with such a dichroic filter equipped makes an evenbrighter electrooptical device.

FIG. 19 diagrammatically illustrates a projector type color displaydevice, as one example of the electronic apparatus, which uses theabove-referenced electrooptical device as a light valve. The generalconstruction of the projector type color display device, in particular,the optical structure thereof, is discussed.

Referring to FIG. 19, a liquid-crystal projector 1100 can include threeliquid-crystal modules, each including the electrooptical device 100having the driving circuit on the TFT array substrate. Theliquid-crystal projector 1100 thus includes light valves 100R, 100G, and100B for RGB colors. When light is emitted from a lamp unit 1102 as awhite light source such as a metal halide lamp in the liquid-crystalprojector 1100, the light is separated into three RGB color beamsthrough three mirrors 1106 and two dichroic mirrors 1108, and the threecolor light beams are then guided to respective light valves 100R, 100G,and 100B. The blue color beam travels along a path longer than those forthe red and green color beams, and to prevent loss, the blue color beamis guided through a relay lens system 1121, composed of an incident lens1122, a relay lens 1123, and an exit lens 1124. The red, green, and bluelight beams respectively color-modulated by the electrooptical devices100R, 100G, and 100B are incident on a dichroic prism 1112. The threecolor images are synthesized, and a synthesized color image is thenprojected by a projection lens 1114 onto a screen 1120.

It should be understood that the present invention is not limited to theabove-discussed embodiment, and is modified within the scope and spiritof the invention described in the specification, and such modifiedversions of the substrate assembly, the test method, the electroopticaldevice, the manufacturing method, and the electronic equipment fallwithin the scope of the present invention.

1. An electrooptical device comprising, on a substrate, a pixelelectrode; at least one of a wiring and an electronic element that drivethe pixel electrode; an integrated circuit which, when mounted on thesubstrate, forms at least a portion of a driving circuit connected to atleast the one of the wiring and the electronic element; andpredetermined trace patterns arranged beneath the integrated circuit. 2.The electrooptical device according to claim 1, the predetermined tracepatterns comprising at least one of a trace pattern that evaluates amanufacturing process, a trace pattern that test the manufacturingprocess, and a trace pattern that monitors the manufacturing process,while being formed in an area of the substrate other thaninterconnection pads to which input and output terminals of the externalintegrated circuit are connected.
 3. An electrooptical devicecomprising, on a substrate, a pixel electrode; at least one of a wiringand an electronic element that drive the pixel electrode; an integratedcircuit which, when mounted on the substrate, forms at least a portionof a driving circuit connected to at least the one of the wiring and theelectronic element; and a bottom circuit arranged beneath the integratedcircuit and embedded together with at least the one of the wiring andthe electronic element.
 4. The electrooptical device according to claim3, the integrated circuit forming a portion of the driving circuit, andthe bottom circuit forming another portion of the driving circuit. 5.The electrooptical device according to claim 4, the wiring comprising adata line and a scanning line, the integrated circuit comprising a dataline driving circuit that drives the data line, and the bottom circuitcomprising a scanning line driving circuit that drives the scanning lineand a sampling circuit that samples a video signal and supplies the dataline with the sampled video signal.
 6. An electrooptical deviceaccording to claim 3, the bottom circuit comprising a test circuit. 7.An electrooptical device according to claim 3, the electronic elementcomprising a first thin-film transistor connected to the pixelelectrode, and the bottom circuit comprising a second thin-filmtransistor which is manufactured through the same manufacturing processas that of the first thin-film transistor.
 8. An electrooptical deviceaccording to claim 3, an insulator being formed between the integratedcircuit and the bottom circuit.
 9. The electrooptical device accordingto claim 1, the integrated circuit being arranged in a peripheral areasurrounding an image display area within which the pixel electrode isarranged.
 10. The electrooptical device according to claim 1, the toplayer of the substrate on which the integrated circuit is to be mountedbeing planarized.
 11. A manufacturing method of manufacturing theelectrooptical device of claim 1, comprising: a first formation step forforming a predetermined trace pattern within a predetermined area on thesubstrate; performing at least one of the test, evaluation, andmonitoring of a manufacturing process in accordance with thepredetermined trace pattern; a second formation step for forming atleast the one of the wiring and the electronic element; and mounting theintegrated circuit on the predetermined area.
 12. A manufacturing methodof manufacturing the electrooptical device of claim 3, comprising:forming a bottom circuit within a predetermined area on the substrate,the one of the wiring and the electronic element, and the pixelelectrode, and mounting the integrated circuit on the predeterminedarea.
 13. The electrooptical device according to claim 1, thepredetermined trace pattern comprising at least one of an alignment markand an identification mark.
 14. An electrooptical device according toclaim 3, the bottom circuit comprising a circuit element, and theelectrooptical device comprising: a lead wiring extending from thecircuit element, and an external circuit connection terminal for thebottom circuit connected to the lead wiring in a portion of thesubstrate not facing the integrated circuit.
 15. An electroopticaldevice, comprising: a substrate; a peripheral circuit embedded in thesubstrate; a first wiring arranged on the substrate; an integratedcircuit comprising a first terminal connected to an interconnectionportion arranged on the first wiring on the substrate; a second wiringwhich extends from the interconnection portion in such a manner that thesecond wiring is routed in a portion of the substrate facing theintegrated circuit; and a first external circuit connection terminalarranged on the second wiring in a portion of the substrate not facingthe integrated circuit; the electrooptical device further comprising, onthe substrate, a pixel electrode, and at least one of a wiring and anelectronic element that drives the pixel electrode, and the integratedcircuit, mounted on the substrate, forming at least a portion of adriving circuit connected to at least the one of the wiring and theelectronic element, and at least one of a predetermined trace patternand a bottom circuit being arranged beneath the integrated circuit.